Photonic integrated circuit (PIC) technology is expected to play an increasingly important role in optical communications, imaging, computing, and sensing with the promise for significant reduction in cost and weight of these systems. Future advancement of this technology is significantly dependent on the ability to develop better scalability, testability, high performance, and cost effectiveness for this technology.
On-chip surface grating coupler (GC) optical I/O interface components are key to every PIC interconnect. The latest developments have resulted in compact GC that efficiently couples light to and from a standard fiber optic. By arranging fibers and optical I/Os in an array configuration and introducing an optical feedback loop, the optical alignment process can become more efficient, but at a cost. Both fiber array and GC optical I/Os should have the same accepted standard pitch of 127 microns (μm), which limits PIC chip density and increases the overall cost. In addition, the existing optical feedback loop configuration does not allow flexible optical interconnects. The problem becomes more severe when a large number of optical I/Os per chip are required since the optical I/O footprint may become prohibitively expensive. In addition, it could prevent wafer-scale automated testing and verification.